Addressing Device Handling Challenges During Expanded Wafer Test

☰ Quick Links

The demand for 5G, IoT, AI, wearables, and self-driving or electric vehicles demands the highest level of semiconductor performance. Research, development, and design of advanced monolithic semiconductors for next technology node is estimated to account for 70-80% of device costs. To cost-effectively meet performance demand targets, the semiconductor industry uses advanced packaging and assembly solutions like 2.5D, 3D, and heterogeneous integration, for combining top technologies from various sources. In 2023, advanced packaging made up about 44% of the IC packaging market and is expected to grow at an 11% CAGR from 2023 to 2029.

Chiplets use 2.5D and 3D stacking to integrate smaller interconnected dies, offering higher integration without more space. However, this approach is costly, as the overall performance is limited by the lowest performing die as the number of dies increases. The test and assembly process for chiplets demands careful handling of components. Adaptable carriers, essential for accommodating various device XYZ dimensions and ensuring compatibility with equipment, are required for nearly every form factor produced by a fab.

The IEEE HiR Roadmap highlights major challenges in traditional chip handling due to varying device sizes and multiple handling stages. Historically, bare die are managed using pocketed solutions like waffle packs, JEDEC trays, tape & reel, and sticky-tape methods such as back-grind tape for film frames. These singulated bare die are prone to issues like brittleness, contamination, cracking, and breaking.

Waffle packs and JEDEC trays transport bare die but limit access to chip edges, crucial for devices with large stay-out zones. Tape & reel strategies have fixed pocket sizes that aren’t suitable for ICs with changing forms or multiple testing. Sticky tapes like back-grind film don’t need custom pockets but restrict reuse since devices can’t be reattached once removed.

Gel-Pak developed a universal chip carrier strategy that eliminates the limitations of molded trays and single-use carrier tapes. Various films and surfaces with numerous microscopic contact points have been created. Less than 2% of the device area contacts the film, and the holding force is independent of the device’s backside surface properties. The holding force can be adjusted for various uses: low tack for in-process handling, medium tack for shipping bare dies, and high tack for packaged devices.

These dry adhesives use surface forces and kinetics to provide strong, controllable, and reliable adhesion, securely holding bare die without pockets. Individual lids for each carrier are not required. The ultra-clean films can be easily converted and laminated into waffle packs, JEDEC trays, and film frames. Pocketless trays can accommodate different sizes and configurations, simplifying overall complexity, inventory management, and costs.

Wafer Tests
Pocketless trays developed by Gel-Pak.

Efficient testing necessitates the use of universal tools and standards. The micro-textured films developed by Gel-Pak improve die handling in high-volume manufacturing, facilitating flexible chip management without the need for custom compartments. Enhanced testing standards and specialized cleaning materials contribute to improved operational equipment effectiveness (OEE). Gel-Pak is dedicated to delivering innovative solutions that optimize yield and improve the handling, testing, and transportation of dies and high-value devices.

Gel-Pak's experienced technical support staff is available to answer your questions related to products or associated applications.

Contact Us!